Digital high speed acquisition system for phase locked loops

Disclosed is a signal generator that includes a memory to store tuning voltage values and offset voltage values. An adder/subtractor circuit is coupled to the memory to produce a sum and a difference of the tuning and offset voltages. A comparator circuit is coupled to the adder/subtractor circuit t...

Full description

Saved in:
Bibliographic Details
Main Authors Williams, Anthony David, Lee, Vincent, Rai, Gursewak Singh
Format Patent
LanguageEnglish
Published 16.06.2020
Subjects
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
CODE CONVERSION IN GENERAL
CODING
DECODING
ELECTRICITY
PULSE TECHNIQUE
Online AccessGet full text

Cover

More Information
Summary:Disclosed is a signal generator that includes a memory to store tuning voltage values and offset voltage values. An adder/subtractor circuit is coupled to the memory to produce a sum and a difference of the tuning and offset voltages. A comparator circuit is coupled to the adder/subtractor circuit to receive a digitized voltage controlled oscillator tuning voltage and to compare the digitized voltage controlled oscillator tuning voltage to the sum and difference of the tuning and offset voltages to produce a window bounded by the sum and difference of the tuning and offset voltages. The comparator circuit is further configured to generate control signals. A steering current circuit is coupled to the comparator circuit to receive the control signals from the comparator circuit and to control a steering current based on the control signals.
Bibliography:Application Number: US201916540577