Non-disruptive clearing of varying address ranges from cache

In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to...

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Bibliographic Details
Main Authors Mak, Pak-kin, Blake, Michael A, Berger, Deanna P. D, Ambroladze, Ekaterina M, Tracy, Guy G, Sonnelitter, III, Robert J, Wilson, Chad G
Format Patent
LanguageEnglish
Published 12.05.2020
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.
Bibliography:Application Number: US201916281132