Methods of forming a transistor and methods of forming an array of memory cells

• Main Authors: Smythe, John A, Hwang, David K, Pandey, Deepak Chandra, Liu, Haitao, Hill, Richard J
• Format: Patent
• Language: English
• Published: 05.05.2020
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

An embodiment of the invention comprises a method of forming a transistor comprising forming a gate construction having an elevationally-outermost surface of conductive gate material that is lower than an elevationally-outer surface of semiconductor material that is aside and above both sides of the gate construction. Tops of the semiconductor material and the conductive gate material are covered with masking material, two pairs of two opposing sidewall surfaces of the semiconductor material are laterally exposed above both of the sides of the gate construction. After the covering, the semiconductor material that is above both of the sides of the gate construction is subjected to monolayer doping through each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs and forming there-from doped source/drain regions above both of the sides of the gate construction.