Combined analog architecture and functionality in a mixed-signal array
A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is con...
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Main Authors | , , , , , , , , , , , |
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Format | Patent |
Language | English |
Published |
28.04.2020
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Subjects | |
Online Access | Get full text |
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Summary: | A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode. |
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Bibliography: | Application Number: US201916420910 |