Merging level cache and data cache units having indicator bits related to speculative execution
Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads...
Saved in:
Main Authors | , , , , , , , |
---|---|
Format | Patent |
Language | English |
Published |
14.04.2020
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Be the first to leave a comment!