Merging level cache and data cache units having indicator bits related to speculative execution

Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads...

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Bibliographic Details
Main Authors Lopez, Pedro, Codina, Enric Gibert, Madriles, Carlos, Latorre, Fernando, Martinez, Raul, Codina, Josep M, Vincente, Alejandro Martinez, Gonzalez, Antonio
Format Patent
LanguageEnglish
Published 14.04.2020
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retires instructions of the speculatively executed threads in the MLC.
Bibliography:Application Number: US201414563839