Memory latency management

Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator...

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Bibliographic Details
Main Authors Ooi, Eng Hun, Fanning, Blaise, Royer, Jr., Robert J
Format Patent
LanguageEnglish
Published 25.02.2020
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
CODE CONVERSION IN GENERAL
CODING
COMPUTING
COUNTING
DECODING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
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Summary:Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.
Bibliography:Application Number: US201815756039