Non-destructive analysis to determine use history of processor

A method and system are provided for chip testing. The method includes selectively deploying a chip for future use or discarding the chip to prevent the future use, responsive to a stress history of the chip determined using a non-destructive test procedure. The test procedure includes ordering each...

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Bibliographic Details
Main Authors Ray, Emily A, Stawiasz, Kevin G, Weger, Alan J, Song, Peilin, Linder, Barry P, Yashchin, Emmanuel, Stellari, Franco, Jenkins, Keith A, Stathis, James H, Robertazzi, Raphael P
Format Patent
LanguageEnglish
Published 04.02.2020
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A method and system are provided for chip testing. The method includes selectively deploying a chip for future use or discarding the chip to prevent the future use, responsive to a stress history of the chip determined using a non-destructive test procedure. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto. The test procedure further includes ranking each of the plurality of patterns based on at least one preceding available pattern to provide a plurality of pattern ranks. The test procedure also includes calculating a sum by summing the plurality of pattern ranks. The sum calculated during an initial performance of the test procedure is designated as a baseline, and the sum calculated during a subsequent performance of the test procedure is compared to a threshold derived from the baseline to determine the stress history of the chip.
Bibliography:Application Number: US201816035032