Forming stacked twin III-V nano-sheets using aspect-ratio trapping techniques

A semiconductor structure that includes: a substrate, a twin vertical punch-through stopper layer structure connected to the substrate, and a plurality of nanosheets connected to and supported by the twin vertical punch-through stopper structure and isolated from the substrate by an insulating diele...

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Bibliographic Details
Main Authors Khojasteh, Mahmoud, Reznicek, Alexander, Hashemi, Pouya, Balakrishnan, Karthik
Format Patent
LanguageEnglish
Published 28.01.2020
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A semiconductor structure that includes: a substrate, a twin vertical punch-through stopper layer structure connected to the substrate, and a plurality of nanosheets connected to and supported by the twin vertical punch-through stopper structure and isolated from the substrate by an insulating dielectric.
Bibliography:Application Number: US201715834721