Disabling cache portions during low voltage operations

Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other...

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Bibliographic Details
Main Authors Chaparro Monferrer, Pedro, De, Vivek, Wilkerson, Christopher, Khellah, Muhammad M, Abella, Jaume, Vera, Xavier, Carretero Casado, Javier, Zhang, Ming, Gonzalez, Antonio
Format Patent
LanguageEnglish
Published 07.01.2020
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
Bibliography:Application Number: US201715621401