Method and apparatus for interrupting memory bank refresh

A memory controller includes a state machine that initiates a memory refresh of a DRAM (having a number of banks) by sending thereto a refresh command. Responsive to receiving the command, the DRAM may perform a per-bank refresh in which individual ones of the banks are refreshed in succession, one...

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Bibliographic Details
Main Authors Notani, Rakesh L, Hsiung, Kai Lun, Fu, Peter
Format Patent
LanguageEnglish
Published 17.12.2019
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory controller includes a state machine that initiates a memory refresh of a DRAM (having a number of banks) by sending thereto a refresh command. Responsive to receiving the command, the DRAM may perform a per-bank refresh in which individual ones of the banks are refreshed in succession, one at a time. Upon receiving a high priority transaction, a determination is made as to the number of memory banks that have currently been refreshed in the per-bank refresh. If the number of banks refreshed is less than a threshold value, the per-bank refresh is aborted.
Bibliography:Application Number: US201816012366