Receiver with cancellation of intrinsic offset from decision feedback equalization to enhance data margin

A receiver is provided that generates a data sampling clock that is offset by clock offset that is a function of a decision feedback equalizer gain to account for a data sampling timing error that would occur without the clock delay.

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Bibliographic Details
Main Authors Sun, Li, Chang, Chia Heng, Chen, Minhan, Deans, Russell, Goudarzi, Hadi
Format Patent
LanguageEnglish
Published 10.12.2019
Subjects
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:A receiver is provided that generates a data sampling clock that is offset by clock offset that is a function of a decision feedback equalizer gain to account for a data sampling timing error that would occur without the clock delay.
Bibliography:Application Number: US201816233647