Receiver with cancellation of intrinsic offset from decision feedback equalization to enhance data margin
A receiver is provided that generates a data sampling clock that is offset by clock offset that is a function of a decision feedback equalizer gain to account for a data sampling timing error that would occur without the clock delay.
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Main Authors | , , , , |
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Format | Patent |
Language | English |
Published |
10.12.2019
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Subjects | |
Online Access | Get full text |
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Summary: | A receiver is provided that generates a data sampling clock that is offset by clock offset that is a function of a decision feedback equalizer gain to account for a data sampling timing error that would occur without the clock delay. |
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Bibliography: | Application Number: US201816233647 |