In-field system test security

A processor, including: a core; system test circuitry, the system test circuitry configured to be locked except during an in-field system test (IFST) mode; IFST control circuitry; and a test interface controller, including: a data interface to receive a test packet; a parser to parse the test packet...

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Bibliographic Details
Main Authors Shah, Neel, Santoni, Amy L, Chakravarty, Sreejit, Mendoza, Oscar, Yap, Kirk S, Neve de Mevergnies, Michael, Rajamani, Ramasubramanian, Iacobovici, Sorin, Gran, Bryan J
Format Patent
LanguageEnglish
Published 26.11.2019
Subjects
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:A processor, including: a core; system test circuitry, the system test circuitry configured to be locked except during an in-field system test (IFST) mode; IFST control circuitry; and a test interface controller, including: a data interface to receive a test packet; a parser to parse the test packet into a key, a signature, and a stored hash-of-hashes; a decryption circuit to decrypt the signature according to the key and to generate a computed hash-of-hashes; a hash circuit to verify the stored hash-of-hashes against the computed hash-of-hashes; and an IFST interface, wherein the test interface controller is to signal the IFST control circuitry to place the system test circuitry in IFST mode.
Bibliography:Application Number: US201715638162