Apparatus and method for efficiently implementing a processor pipeline

Various different embodiments of the invention are described including: (1) a method and apparatus for intelligently allocating threads within a binary translation system; (2) data cache way prediction guided by binary translation code morphing software; (3) fast interpreter hardware support on the...

Full description

Saved in:
Bibliographic Details
Main Authors Neelakantam, Naveen, Schuchman, Ethan, Hyuseinova Seidahmedova, Mirem, Topp, Jaroslaw, Stellpflug, Gregor, Lai, Patrick P, Fryman, Joshua B, Khartikov, Denis M, Pavlou, Demos, Knies, Allan D, Kelm, John H, Keppel, David, Xekalakis, Polychronis
Format Patent
LanguageEnglish
Published 10.09.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:Various different embodiments of the invention are described including: (1) a method and apparatus for intelligently allocating threads within a binary translation system; (2) data cache way prediction guided by binary translation code morphing software; (3) fast interpreter hardware support on the data-side; (4) out-of-order retirement; (5) decoupled load retirement in an atomic OOO processor; (6) handling transactional and atomic memory in an out-of-order binary translation based processor; and (7) speculative memory management in a binary translation based out of order processor.
Bibliography:Application Number: US201414319265