Memory controller, semiconductor memory system and operating method thereof
An operation method of a memory controller may include performing a first decoding operation to a message of an internal region included in a codeword received from a semiconductor memory device by using an internal parity, wherein the message and the internal parity are included in the internal reg...
Saved in:
Main Authors | , |
---|---|
Format | Patent |
Language | English |
Published |
27.08.2019
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Be the first to leave a comment!