Memory controller, semiconductor memory system and operating method thereof

An operation method of a memory controller may include performing a first decoding operation to a message of an internal region included in a codeword received from a semiconductor memory device by using an internal parity, wherein the message and the internal parity are included in the internal reg...

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Bibliographic Details
Main Authors Kim, Dae-Sung, Ha, Jeong-Seok
Format Patent
LanguageEnglish
Published 27.08.2019
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
CODE CONVERSION IN GENERAL
CODING
COMPUTING
COUNTING
DECODING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
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Summary:An operation method of a memory controller may include performing a first decoding operation to a message of an internal region included in a codeword received from a semiconductor memory device by using an internal parity, wherein the message and the internal parity are included in the internal region in a matrix form; and performing a second decoding operation to the internal region, to which the first decoding operation is performed, by using an outer parity of an outer region.
Bibliography:Application Number: US201715627541