Semiconductor package with plateable encapsulant and a method for manufacturing the same
A package which comprises a first encapsulant configured so that electrically conductive material is plateable thereon, and a second encapsulant configured so that electrically conductive material is not plateable thereon.
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Main Authors | , , , , , , , , |
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Format | Patent |
Language | English |
Published |
27.08.2019
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Subjects | |
Online Access | Get full text |
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Summary: | A package which comprises a first encapsulant configured so that electrically conductive material is plateable thereon, and a second encapsulant configured so that electrically conductive material is not plateable thereon. |
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Bibliography: | Application Number: US201715448018 |