Field-effect transistor placement optimization for improved leaf cell routability

A processor-implemented method for automatically generating a layout of a cell of a semiconductor circuit is provided herein. The processor-implemented method includes reading a netlist of the cell. The netlist includes a description of internal electrical nets connecting electrical components of th...

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Bibliographic Details
Main Authors Leefken, Iris Maria, Werner, Tobias T, Penth, Silke, Stetter, Michael
Format Patent
LanguageEnglish
Published 27.08.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A processor-implemented method for automatically generating a layout of a cell of a semiconductor circuit is provided herein. The processor-implemented method includes reading a netlist of the cell. The netlist includes a description of internal electrical nets connecting electrical components of the cell with each other. The processor-implemented method assigning a weight to an internal net of the internal electrical nets and placing the electrical components in an area of the semiconductor circuit based on the netlist and the weight to generate the layout of the cell of the semiconductor circuit.
Bibliography:Application Number: US201715586851