Semiconductor fabrication design rule loophole checking for design for manufacturability optimization

• Main Authors: Tian, Kehan, Shao, Dongbing, Lin, Chieh-Yu, Xu, Zheng
• Format: Patent
• Language: English
• Published: 27.08.2019
• Subjects: APPARATUS SPECIALLY ADAPTED THEREFOR; CALCULATING; CINEMATOGRAPHY; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; ELECTROGRAPHY; HOLOGRAPHY; MATERIALS THEREFOR; ORIGINALS THEREFOR; PHOTOGRAPHY; PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES; PHYSICS

Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.