Integrated confirmation queues

According to one general aspect, an apparatus may include a cache pre-fetcher configured to predict data to be retrieved from a memory system. The cache pre-fetcher may include a pattern predictor circuit and a confirmation queue circuit. The pattern predictor circuit may be configured to predict a...

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Bibliographic Details
Main Authors Ghiya, Ankit, Brekelbaum, Edward A
Format Patent
LanguageEnglish
Published 20.08.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:According to one general aspect, an apparatus may include a cache pre-fetcher configured to predict data to be retrieved from a memory system. The cache pre-fetcher may include a pattern predictor circuit and a confirmation queue circuit. The pattern predictor circuit may be configured to predict a series of memory addresses to be pre-fetched from the memory system. The confirmation queue circuit may be configured to: maintain a windowed confirmation queue of predicted memory addresses, compare a requested memory address against the predicted memory addresses, and, if the requested memory address is included in the predicted memory addresses, indicate that a successful pre-fetch has occurred.
Bibliography:Application Number: US201715665401