Highly flexible performance counter and system debug module

According to one general aspect, an apparatus may include a plurality of performance and debug monitoring circuits (PDMCs). Each performance and debug monitoring circuit (PDMC) may include an input stage, a combinatorial stage, and a counter. The input stage may be configured to receive a plurality...

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Bibliographic Details
Main Authors Rubin, Lawrence H, Tannenbaum, David C
Format Patent
LanguageEnglish
Published 20.08.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:According to one general aspect, an apparatus may include a plurality of performance and debug monitoring circuits (PDMCs). Each performance and debug monitoring circuit (PDMC) may include an input stage, a combinatorial stage, and a counter. The input stage may be configured to receive a plurality of input signals, wherein the input signals include: signals from other performance and debug monitoring circuits, signals from combinatorial logic circuits, and configuration values. The combinatorial stage may be configured to perform one or more logical operations on a selected sub-set of the input signals. The counter may be configured to increment based, at least in part, upon a result of the combinatorial stage.
Bibliography:Application Number: US201715464334