Back gate tuning circuits

The present disclosure generally relates to semiconductor structures and, more particularly, to back gate tuning circuits and methods of manufacture. The method includes applying a voltage to a back gate of a device; and selectively controlling the applied voltage to deactivate at least one trap wit...

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Bibliographic Details
Main Authors Höntschel, Jan, Jüttner, Maximilian, Otto, Michael
Format Patent
LanguageEnglish
Published 20.08.2019
Subjects
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:The present disclosure generally relates to semiconductor structures and, more particularly, to back gate tuning circuits and methods of manufacture. The method includes applying a voltage to a back gate of a device; and selectively controlling the applied voltage to deactivate at least one trap within an insulating layer of the device to reduce noise contribution from the at least one trap.
Bibliography:Application Number: US201815887417