Memory device

• Main Authors: Shin, Taek Soo, You, Jang Hyun, Lee, Sung Yun, Park, Jin Taek
• Format: Patent
• Language: English
• Published: 16.07.2019
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.