SRAM margin recovery during burn-in

Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a "zero" state bit with in the bi-stable flip-flop of the SRAM. Raising...

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Bibliographic Details
Main Authors Huott, William V, McPadden, Adam J, Srinivasan, Uma, Wu, Stephen, Kothandaraman, Chandrasekharan
Format Patent
LanguageEnglish
Published 25.06.2019
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a "zero" state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the "zero" state bit and selective transistor biasing, skews the "zero" state bit towards the complementary "one" state bit. This induces an increase voltage thresholds of the identified SRAM cells.
Bibliography:Application Number: US201815902065