Memory sharing for buffered macro-pipelined data plane processing in multicore embedded systems

Disclosed are an apparatus and method of operating and allocating a shared memory between various applications operating via a processing computing platform. One example may include receiving a first buffer context switch request message from a first application operating via a processor, transmitti...

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Bibliographic Details
Main Author McKown, Russell C
Format Patent
LanguageEnglish
Published 18.06.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Disclosed are an apparatus and method of operating and allocating a shared memory between various applications operating via a processing computing platform. One example may include receiving a first buffer context switch request message from a first application operating via a processor, transmitting a first buffer context switch flag to the processor operating the application confirming the first buffer context switch request was received, receiving a second buffer context switch request from a second application with a different processing cycle operating via the processor and transmitting a second buffer context switch flag to the processor operating the second application confirming the second buffer context switch request was received. Once the applications have been identified and confirmed, a synchronization operation may be performed to create a shared number of memory units between at least two different buffers and provide the shared memory units to the first application and the second application.
Bibliography:Application Number: US201615390624