Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same

• Main Authors: Orimoto, Takashi, Sai, Akihisa, Alsmeier, Johann, Zhang, Tong, Yada, Shinsuke, Nagamine, Sayako, Kai, James
• Format: Patent
• Language: English
• Published: 21.05.2019
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.