Phase locked loop

• Main Author: Saric, Tarik
• Format: Patent
• Language: English
• Published: 07.05.2019
• Subjects: ANALOGOUS ARRANGEMENTS USING OTHER WAVES; AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRONIC CIRCUITRY; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; ELECTRICITY; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION ORRERADIATION OF RADIO WAVES; MEASURING; PHYSICS; RADIO DIRECTION-FINDING; RADIO NAVIGATION; TESTING

A phase locked loop for generating a frequency chirp is disclosed. The phase locked loop comprises a phase frequency detector configured to receive a reference frequency signal at a first input, a low pass filter configured to receive a current from the phase frequency detector at a filter input, and to output a control voltage, a voltage controlled oscillator configured to generate the frequency chirp at an output in response to receiving the control voltage, a feedback path connecting the output of the voltage controlled oscillator to a second input of the phase frequency detector, the feedback path comprising a frequency divider; and a timing module configured to generate a reset pulse. The low pass filter comprises a plurality of capacitors connected in parallel between the filter input and a common voltage line; and a voltage source configured to generate an initial control voltage. The voltage source is switchably connected to a node between a first capacitor of the plurality of capacitors and the common voltage line, and is connected to the node during a chirp reset mode defined by the reset pulse such that the voltage at the node is substantially equalized to the initial control voltage.