Apparatus and method for a coherent, efficient, and configurable cyclic redundancy check retry implementation for synchronous dynamic random access memory

Embodiments of the invention provide an apparatus and method for a coherent, efficient, and configurable cyclic check redundancy retry implementation for synchronous dynamic random access memory. The process includes storing write commands as groups of bursts in a storage location where those comman...

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Bibliographic Details
Main Authors Banerjee, Bikram, MacLaren, John Michael, Hughes, Anne Rodgers
Format Patent
LanguageEnglish
Published 07.05.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:Embodiments of the invention provide an apparatus and method for a coherent, efficient, and configurable cyclic check redundancy retry implementation for synchronous dynamic random access memory. The process includes storing write commands as groups of bursts in a storage location where those commands are stored at least until a time frame has passed for receiving a corresponding cyclic redundancy check failure message. In some embodiments, the process includes retrying corresponding groups of bursts after receiving a failure message where retried groups of bursts are given priority over other memory access commands. In some embodiments, when a read command is received corresponding to a write command that is not beyond the relevant time frame the read command will also be held back from execution until the corresponding time frame has passed without notification of cyclic redundancy check value failure.
Bibliography:Application Number: US201715808852