Multi-stage pattern recognition in circuit designs

An identification of a first area of an IC design surrounding a failure component is received; and, in response, a smaller portion of the first area is selected. The smaller portion also surrounds the failure component, is smaller than the first area, and contains less circuit components than the fi...

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Bibliographic Details
Main Authors Schroeder, Uwe Paul, Batarseh, Fadi, Krishnamoorthy, Karthik, Omran, Ahmed
Format Patent
LanguageEnglish
Published 02.04.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:An identification of a first area of an IC design surrounding a failure component is received; and, in response, a smaller portion of the first area is selected. The smaller portion also surrounds the failure component, is smaller than the first area, and contains less circuit components than the first area. The smaller portion is matched to other areas of the IC design to identify potentially undesirable patterns of the IC design that are the same size as the first area. Additionally, the potentially undesirable patterns are grouped into pattern categories, the pattern categories are matched to known good pattern categories, and the known good patterns are removed from the potentially undesirable patterns to leave potential failure patterns. The potential failure patterns of the IC design are then output.
Bibliography:Application Number: US201715602810