High performance interconnect

• Main Authors: Spink, Aaron T, Johnson, Simon P, Fahim, Bahaa, Nale, William Harry, Swanson, Jeffrey C, Geetha, Vedaraman, Spagna, Fulvio, Das, Abhishek, Kumar, Arvind A, Shah, Rahul R, Blankenship, Robert G, Gupta, Ashish, Jue, Darren S, Iyer, Sitaraman V, Safranek, Robert J, Beers, Robert H, Willey, Jeff, Ramanujan, Raj K, Hum, Herbert H, Dhillon, Yuvraj S, Liu, Yen-Cheng, Sharma, Debendra Das, Iyer, Venkatraman, Maddox, Robert A
• Format: Patent
• Language: English
• Published: 02.04.2019
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; PHYSICS; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.