Split-level history buffer in a computer processing unit

A split level history buffer in a central processing unit is provided. A history buffer is partitioned into a first portion and a second portion, wherein the first portion includes a first tagged instruction. A result is generated for the first tagged instruction. A determination whether a second ta...

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Bibliographic Details
Main Authors Nguyen, Dung Q, Terry, David R, Le, Hung Q
Format Patent
LanguageEnglish
Published 26.03.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A split level history buffer in a central processing unit is provided. A history buffer is partitioned into a first portion and a second portion, wherein the first portion includes a first tagged instruction. A result is generated for the first tagged instruction. A determination whether a second tagged instruction is to be stored in the first portion of the history buffer is made. Responsive to the determination that the second tagged instruction is to be stored in the first portion of the history buffer, the first tagged instruction and the generated result for the first tagged instruction is written to the second portion of the history buffer.
Bibliography:Application Number: US201514740694