Mixed P/N MOS array layout and methods of forming the same

A semiconductor structure is disclosed that includes a p-channel metal-oxide semiconductor (PMOS) array having a first set of oxide diffusion layer (OD) structures, an n-channel metal-oxide semiconductor (NMOS) array having a second set of OD structures, and a dummy buffer zone surrounding the PMOS...

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Bibliographic Details
Main Authors Lien, Bei-Shing, Horng, Jaw-Juinn
Format Patent
LanguageEnglish
Published 15.01.2019
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A semiconductor structure is disclosed that includes a p-channel metal-oxide semiconductor (PMOS) array having a first set of oxide diffusion layer (OD) structures, an n-channel metal-oxide semiconductor (NMOS) array having a second set of OD structures, and a dummy buffer zone surrounding the PMOS and NMOS arrays. The semiconductor structure has a uniform spacing between OD structures in the first and second sets of OD structures and between the PMOS and NMOS array, such that no dummy buffer zone is included between the PMOS array and the NMOS array.
Bibliography:Application Number: US201715638505