Efficient memory virtualization in multi-threaded processing units

A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical...

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Bibliographic Details
Main Authors Hairgrove, Mark, Fahs, Brian, Duluk, Jr., Jerome F, Barrow-Williams, Nick, Deming, James Leroy, Purcell, Timothy John, Dunning, Lucien
Format Patent
LanguageEnglish
Published 01.01.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.
Bibliography:Application Number: US201213660799