Loading data for iterative evaluation through SIMD registers
Executable code is generated for processing a request including a predicate associated with a column of a database table. The executable code defines how to process data through a register at the processor associated with single instructions on multiple data. When a number of bit values of the regis...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
25.12.2018
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Subjects | |
Online Access | Get full text |
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Summary: | Executable code is generated for processing a request including a predicate associated with a column of a database table. The executable code defines how to process data through a register at the processor associated with single instructions on multiple data. When a number of bit values of the register at the processor is not an aliquot part of a count of rows in the column of the database table, a new column is loaded in the main memory to include the column of the database table and additional number of data elements. The number of bit values of a register section of the register is an aliquot part of a number of elements of the new column. The new loaded column is evaluated iteratively to determine result bit vectors to be loaded in the register. At the processor, result data is determined to correspond to the evaluated section. |
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Bibliography: | Application Number: US201615261886 |