Eliminating redundant store instructions from execution while maintaining total store order

A processor includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, and a binary translator. The binary translator includes circuitry to identify a redundant store in the instruction stream, ma...

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Bibliographic Details
Main Authors Mekkat, Vineeth, Wu, Youfeng, Chou, Ching-Tsun, Margulis, Oleg
Format Patent
LanguageEnglish
Published 06.11.2018
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A processor includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, and a binary translator. The binary translator includes circuitry to identify a redundant store in the instruction stream, mark the start and end of a region of the instruction stream with the redundant store, remove the redundant store, and store an amended instruction stream with the redundant store removed.
Bibliography:Application Number: US201615175899