Synchronous dynamic random access memory (SDRAM) device, memory controller for same, and method of operating same

A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mi...

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Bibliographic Details
Main Authors Shin, Seung-Jun, Oh, Tae-Young
Format Patent
LanguageEnglish
Published 30.10.2018
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.
Bibliography:Application Number: US201715690379