Efficient power management of UART interface
Methods and apparatus relating to efficient and/or robust link power management of a UART (Universal Asynchronous Receiver/Transmitter) interface are described. In an embodiment, logic causes a link to enter into a low power consumption state in response to a message exchange over data lines of a UA...
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Main Authors | , , , |
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Format | Patent |
Language | English |
Published |
16.10.2018
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Subjects | |
Online Access | Get full text |
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Summary: | Methods and apparatus relating to efficient and/or robust link power management of a UART (Universal Asynchronous Receiver/Transmitter) interface are described. In an embodiment, logic causes a link to enter into a low power consumption state in response to a message exchange over data lines of a UART (Universal Asynchronous Receiver/Transmitter) interface. The message exchange over the data lines of the UART interface is followed by a modification to one or more flow control signals coupled to the UART interface. Other embodiments are also disclosed. |
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Bibliography: | Application Number: US201414499107 |