Instruction and logic for register based hardware memory renaming

A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a dependency between a store instruction and a load instruction, and a second logic to assign a memory renaming (MRN) register to the store inst...

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Main Authors Yanover, Igor, Leifman, George, Kluchnikov, Andrey, Garifullin, Kamil, Kryukov, Pavel I, Gerber, Alex, Stark, Jared W, Rappoport, Lihu, Shwartsman, Stanislav, Sperber, Zeev
Format Patent
LanguageEnglish
Published 09.10.2018
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a dependency between a store instruction and a load instruction, and a second logic to assign a memory renaming (MRN) register to the store instruction and the load instruction based on the identified dependency. Further, the memory rename module may include a third logic to copy, based on the assigned MRN register, information in a first logical register associated with the store instruction directly to a second logical register associated with the load instruction.
Bibliography:Application Number: US201414581268