3D vertical FET with top and bottom gate contacts
A semiconductor device includes a vertical transistor having a gate structure disposed about a channel region thereof. The vertical transistor has a top side above the gate structure and a bottom side below the gate structure. The top side includes metallization structures having a connection to the...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
11.09.2018
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Subjects | |
Online Access | Get full text |
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