3D vertical FET with top and bottom gate contacts

A semiconductor device includes a vertical transistor having a gate structure disposed about a channel region thereof. The vertical transistor has a top side above the gate structure and a bottom side below the gate structure. The top side includes metallization structures having a connection to the...

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Bibliographic Details
Main Authors Anderson, Brent A, Chu, Albert M
Format Patent
LanguageEnglish
Published 11.09.2018
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A semiconductor device includes a vertical transistor having a gate structure disposed about a channel region thereof. The vertical transistor has a top side above the gate structure and a bottom side below the gate structure. The top side includes metallization structures having a connection to the vertical transistor on the top side. The bottom side includes metallization structures having a connection to the vertical transistor on the bottom side, and the bottom side includes a power rail and a ground rail.
Bibliography:Application Number: US201715676461