Memory array and link error correction in a low power memory sub-system

A method of memory array and link error correction in a low power memory sub-system includes embedding error correction code (ECC) parity bits within unused data mask bits during a normal write operation and during a read operation. The method also includes embedding the ECC parity bits in a mask wr...

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Bibliographic Details
Main Authors Suh, Jungwon, West, David Ian
Format Patent
LanguageEnglish
Published 28.08.2018
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A method of memory array and link error correction in a low power memory sub-system includes embedding error correction code (ECC) parity bits within unused data mask bits during a normal write operation and during a read operation. The method also includes embedding the ECC parity bits in a mask write data byte corresponding to an asserted data mask bit during a mask write operation.
Bibliography:Application Number: US201514859063