Packaged semiconductor device with interior polygonal pads

Embodiments of a packaged semiconductor device with interior polygon pads are disclosed. One embodiment includes a semiconductor chip and a package structure defining a rectangular boundary and having a bottom surface that includes interior polygonal pads exposed at the bottom surface of the package...

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Bibliographic Details
Main Authors Groenhuis, Roelf A. J, Lloyd, Clifford J, Wan, Chi Hoo, Lam, Kan Wae, Wong, Fei Ying
Format Patent
LanguageEnglish
Published 21.08.2018
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Embodiments of a packaged semiconductor device with interior polygon pads are disclosed. One embodiment includes a semiconductor chip and a package structure defining a rectangular boundary and having a bottom surface that includes interior polygonal pads exposed at the bottom surface of the package structure and located on a centerline of the bottom surface of the package structure and edge polygonal pads exposed at the bottom surface of the package structure, located at an edge of the rectangular boundary, and including one edge polygonal pad in the vicinity of each corner of the rectangular boundary. The interior polygonal pads are configured such that a line running between at least one vertex of each of the interior polygonal pads is parallel to an edge of the rectangular boundary of the package structure.
Bibliography:Application Number: US201614990304