Low power scheme for bit flipping low density parity check decoder

A method of power saving for a low-density parity check (LDPC) decoder includes: during each decoding iteration, determining a syndrome weight; and using the determined syndrome weight to set an optimal clock frequency for the LDPC decoding. The LDPC decoder applies hard decision decoding using a bi...

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Bibliographic Details
Main Author Weng, Chen-Yu
Format Patent
LanguageEnglish
Published 14.08.2018
Subjects
BASIC ELECTRONIC CIRCUITRY
CODE CONVERSION IN GENERAL
CODING
DECODING
ELECTRICITY
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Summary:A method of power saving for a low-density parity check (LDPC) decoder includes: during each decoding iteration, determining a syndrome weight; and using the determined syndrome weight to set an optimal clock frequency for the LDPC decoding. The LDPC decoder applies hard decision decoding using a bit-flipping algorithm. When it is determined that the syndrome weights begin to overlap, the method further includes: performing one more iteration in hard decision hard decoding mode; providing a power boost to the LDPC decoder; and switching to hard decision soft decoding mode.
Bibliography:Application Number: US201615073606