Circuits for and methods of reducing power consumed by routing clock signals in an integrated
A circuit for reducing power consumed by routing clock signals in an integrated circuit is described. The circuit comprises a clock routing network comprising a clock row coupled to receive an input clock signal having a first clock frequency and a plurality of clock branches coupled to the clock ro...
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| Main Authors | , |
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| Format | Patent |
| Language | English |
| Published |
14.08.2018
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| Subjects | |
| Online Access | Get full text |
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| Abstract | A circuit for reducing power consumed by routing clock signals in an integrated circuit is described. The circuit comprises a clock routing network comprising a clock row coupled to receive an input clock signal having a first clock frequency and a plurality of clock branches coupled to the clock row; and a plurality of circuit blocks coupled to the plurality of clock branches, each circuit block having a clock conversion circuit and a register; wherein the clock conversion circuit is programmable to generate clock pulses of an internal clock signal, coupled to the register, having a second frequency that is greater than the first frequency. A method of reducing power consumed by routing clock signals in an integrated circuit is also disclosed. |
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| AbstractList | A circuit for reducing power consumed by routing clock signals in an integrated circuit is described. The circuit comprises a clock routing network comprising a clock row coupled to receive an input clock signal having a first clock frequency and a plurality of clock branches coupled to the clock row; and a plurality of circuit blocks coupled to the plurality of clock branches, each circuit block having a clock conversion circuit and a register; wherein the clock conversion circuit is programmable to generate clock pulses of an internal clock signal, coupled to the register, having a second frequency that is greater than the first frequency. A method of reducing power consumed by routing clock signals in an integrated circuit is also disclosed. |
| Author | Devlin, Benjamin S Ganusov, Ilya K |
| Author_xml | – fullname: Ganusov, Ilya K – fullname: Devlin, Benjamin S |
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| Notes | Application Number: US201514792953 |
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| RelatedCompanies | Xilinx, Inc |
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| Snippet | A circuit for reducing power consumed by routing clock signals in an integrated circuit is described. The circuit comprises a clock routing network comprising... |
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| SubjectTerms | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| Title | Circuits for and methods of reducing power consumed by routing clock signals in an integrated |
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