Circuits for and methods of reducing power consumed by routing clock signals in an integrated

A circuit for reducing power consumed by routing clock signals in an integrated circuit is described. The circuit comprises a clock routing network comprising a clock row coupled to receive an input clock signal having a first clock frequency and a plurality of clock branches coupled to the clock ro...

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Bibliographic Details
Main Authors Ganusov, Ilya K, Devlin, Benjamin S
Format Patent
LanguageEnglish
Published 14.08.2018
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A circuit for reducing power consumed by routing clock signals in an integrated circuit is described. The circuit comprises a clock routing network comprising a clock row coupled to receive an input clock signal having a first clock frequency and a plurality of clock branches coupled to the clock row; and a plurality of circuit blocks coupled to the plurality of clock branches, each circuit block having a clock conversion circuit and a register; wherein the clock conversion circuit is programmable to generate clock pulses of an internal clock signal, coupled to the register, having a second frequency that is greater than the first frequency. A method of reducing power consumed by routing clock signals in an integrated circuit is also disclosed.
Bibliography:Application Number: US201514792953