Low defect III-V semiconductor template on porous silicon

A method of forming a semiconductor on a porous semiconductor structure. The method may include forming a stack, the stack includes (from bottom to top) a substrate, a base silicon layer, a thick silicon layer, and a thin silicon layer, where the thin silicon layer and the thick silicon layer are re...

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Bibliographic Details
Main Authors Schepis, Dominic J, Fogel, Keith E, Reznicek, Alexander, de Souza, Joel P
Format Patent
LanguageEnglish
Published 24.07.2018
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A method of forming a semiconductor on a porous semiconductor structure. The method may include forming a stack, the stack includes (from bottom to top) a substrate, a base silicon layer, a thick silicon layer, and a thin silicon layer, where the thin silicon layer and the thick silicon layer are relaxed; converting the thick silicon layer into a porous silicon layer using a porousification process; and forming a III-V layer on the thin silicon layer, where the III-V layer is relaxed, the thin silicon layer is strained, and the porous silicon layer is partially strained.
Bibliography:Application Number: US201514645449