Semiconductor device having biasing structure for self-isolating buried layer and method therefor

A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. Trench isolation portions extend...

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Bibliographic Details
Main Authors Greenwood, Bruce, Hose, Sallie, Suwhanov, Agajan, Agam, Moshe, Janssens, Johan Camiel Julia
Format Patent
LanguageEnglish
Published 17.07.2018
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Summary:A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. Trench isolation portions extend from the first major surface and terminate within the semiconductor region to define an active region. An insulated trench structure is laterally disposed between the trench isolation portions, terminates within the floating buried doped region, and defines a first portion and a second portion of the active region. A biasing semiconductor device is within the first portion, and a functional semiconductor device is within the second portion. The biasing semiconductor device is adapted to set a potential of the floating buried doped region and adapted to divert parasitic currents away from the functional semiconductor device.
Bibliography:Application Number: US201715497443