Memory device for performing multi-core access to bank groups

A memory device has a burst length "b", performs "k" core accesses per command, and receives a command, where "b" is an integer of at least 2 and "k" is an integer of at least 2 and at most "b". The memory device includes a memory cell array includin...

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Bibliographic Details
Main Authors Oh, Tae Young, Song, Ho Sung
Format Patent
LanguageEnglish
Published 26.06.2018
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory device has a burst length "b", performs "k" core accesses per command, and receives a command, where "b" is an integer of at least 2 and "k" is an integer of at least 2 and at most "b". The memory device includes a memory cell array including a plurality of bank groups, a plurality of bank group control units respectively corresponding to the plurality of bank groups, each of the bank group control units configured to generate a multiplexer control signal for selecting part of data read from a corresponding bank group, and a multiplexer configured to sequentially output data read from the plurality of bank groups according to the multiplexer control signal output from the plurality of bank group control units. Data items included in output data of the multiplexer have a same time space.
Bibliography:Application Number: US201615205038