Planarization method for semiconductor structure having memory modules

• Main Authors: LIU, HSIN-JUNG, LI, KUN-JU, LIN, JENIEH, HOU, CHAUUNG, CHAN, ANG
• Format: Patent
• Language: Chinese; English
• Published: 01.02.2024
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

A planarization method for semiconductor structure having memory modules is provided. A dielectric layer is formed on a substrate structure having memory modules, and a contour surface of the dielectric layer has a plurality of protrusions respectively corresponding to the memory modules. A mask layer is conformally formed on the contour surface and the mask layer includes top portions that respectively cover the top surfaces of the protrusions, wherein the mask layer and the dielectric layer have a polishing selectivity. Then, the top portions of the mask layer are removed, so that a plurality of openings is formed on the mask layer to respectively expose the top surfaces of the protrusions. Then, the mask layer is used as a mask, to at least remove the protrusions exposed through the opening. Finally, the mask layer is removed and portion of the dielectric layer is polished, to make the dielectric layer has a substantially planar second surface, wherein a spacing is between the second surface and the memory