Memory cell, memory cell array and method of operating memory cell

• Main Authors: LEE, CHIA-FU, SHIH, YIUN, LIN, HON-JARN
• Format: Patent
• Language: Chinese; English
• Published: 21.12.2023
• Subjects: CALCULATING; COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; IMAGE DATA PROCESSING OR GENERATION, IN GENERAL; INFORMATION STORAGE; PHYSICS; STATIC STORES

A memory cell includes a memory circuit and a multiplier circuit. The multiplier circuit includes an output node configured to output the output signal, a first transistor and an initialization circuit. The first transistor is coupled to the output node and the memory circuit, and is configured to receive at least the second signal. The initialization circuit is coupled to the first transistor by the output node, and is configured to initialize the multiplier circuit in response to at least a third signal or a fourth signal. The memory circuit is configured to store a first value of a first signal of a first storage node. The multiplier circuit is coupled to the memory circuit. The multiplier circuit is configured to generate an output signal in response to the first signal and a second signal. The output signal corresponds to a product of the first signal and the second signal.